1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices such as, e.g., hetero-FETs (HFETs) and high electron mobility transistors (HEMTs) operating at high frequencies.
2. Background Art
Japanese Laid-Open Patent Publication No. H02-012838 discloses a technique in which an opening is formed in an SiO2 layer on a substrate and then a gate electrode is formed on the area of the substrate exposed by the opening. This opening in the SiO2 layer is formed using a patterned resist having a pattern which defines the opening. As a result, the gate electrode is formed to have a width which is equal to the width of the resist pattern.
It is desirable that a process for forming a gate electrode on a semiconductor layer can reduce the gate length while reducing damage to the surface of the semiconductor layer. A reduction in the gate length requires a reduction in the width of the gate electrode. In order to reduce the width of the gate electrode, dry etching is typically used to form the insulating layer pattern for forming the gate electrode.
It has been found, however, that the plasma associated with the dry etching causes damage to the surface of the semiconductor layer. In order to avoid this, wet etching may be used to form the insulating layer pattern for forming the gate electrode. However, it is difficult to form fine features by wet etching, although damage to the surface of the semiconductor layer can be reduced.
Since the technique disclosed in the above publication forms a gate electrode having a width equal to the width of the resist pattern, a high performance exposure apparatus is required to reduce the width of the gate electrode.